11

1772E–DRMSD–10-Apr-06

ATSAM9708

11. Timing Diagrams

All timing conditions: V

with 220 ohms pull-up, 30 pF capacitance; signal PC_IRQ with 470 ohms pull-down, 30 pF

capacitance; all other outputs except X2 and LFT load capacitance = 30 pF. All timings refer to

t

the frequency at pin X1; therefore, t

The maximum crystal frequency/clock frequency at X1 is 12.288 MHz (48 kHz sampling rate).

11.1

PC Host Interface

Figure 11-1. Host Interface Read Cycle

Note:

PC_D[15:8] valid only if PC_A[2:1] = 10.

Figure 11-2. Host Interface Write Cycle

Note:

PC_D[15:8] valid only if PC_A[2:1] = 10.

PC_A[2:0]

PC_CS

PC_RD

PC_ READY

PC_IO16

PC_D[15:0]

PC_A[2:0]

PC_CS

PC_WR

PC_ READY

PC_IO16

PC_D[15:0]