18

1772E–DRMSD–10-Apr-06

ATSAM9708

Figure 13-3. Refresh Cycle (RAS Only)

Note:

1. See Table 12-1 on page 16.

The following points should be noted:

•

The multiplexed CAS, RAS addressing can support memory DRAM chips up to 16 Mbits x N as long as the number of

row address lines and column address lines are identical. For example, device type 416C1200 is supported because it

is a 1M x 16 organization with 10-bit row and 10-bit column. Device type 416C1000 is not supported because it is a 1M

x 16 organization with 12-bit row and 8-bit column.

•

The signal WOE is normally not used for DRAM connection. It is represented only for reference purposes.

RAS

counter

(1)

DRA[11:0]

Table 13-1.

External DRAM Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

t

RC

Read/Write/Refresh cycle

6 x t

CK

ns

Access time from RAS

ns

Access time from CAS

ns

t

OFF

CAS high to output Hi-Z

2 x t

ns

RAS precharge time

ns

RAS pulse width

ns

t

CAS

CAS pulse width

3 x t

ns

RAS to CAS delay time

ns

t

CRP

CAS to RAS precharge time

2 x t

ns

t

ASR

Row address setup time

t

ns

Row address hold time

ns

t

ASC

Column address setup time

t

ns

t

CAH

Column address hold time

3 x t

ns

Write command set-up time

ns

t

WCH

Write command hold time

3 x t

CK

ns

t

DS

Write data set-up time

2 x t

CK

ns

Write data hold time

ns

Refresh counter average period

(12-bit counter)

ns