16

1772E–DRMSD–10-Apr-06

ATSAM9708

12.2.1

Basic Notes on SDRAM Timing

• RESET should be held low at least 100 µs (SDRAM timing requirement on idle cycles)

• SDRAM mode is fixed to sequential, burst length = 1, CAS latency 2, standard operation,

programmed write burst length.

• SDRAM cycles for read: NOP - ACTIVE - NOP - READ AUTO PRECHARGE - NOP - NOP.

• SDRAM cycles for write: NOP - ACTIVE - NOP - WRITE AUTO PRECHARGE - NOP -

NOP

• SDRAM cycles for refresh: NOP - AUTO REFRESH - NOP - NOP - NOP - NOP

Note:

Valid for DRAM and SDRAM unless otherwise stated.

Table 12-1.

Signal

Value at RAS Time

Value at CAS Time

WA0/DRA0

WA0

WA9

WA1/DRA1

WA1

WA10

WA2/DRA2

WA2

WA11

WA3/DRA3

WA3

WA12

WA4/DRA4

WA4

WA13

WA5/DRA5

WA5

WA14

WA6/DRA6

WA6

WA15

WA7/DRA7

WA7

WA16

WA8/DRA8

WA8

WA17

WA18/DRA9

WA18

WA19 (DRAM)

Don’t care (SDRAM)

WA20/DRA10

WA20

WA21 (DRAM)

High (SDRAM)

WA22/DRA11

WA22

WA23 (DRAM)

Don’t care (SDRAM)