4

1772E–DRMSD–10-Apr-06

ATSAM9708

Notes:

1. MIDI and Audio group pins are powered by V

2. These pins have alternate functions as GPIO pins (general-purpose input/output pins). See ”General-purpose Input/Output

Routing” on page 24 for more details.

Table 3-3.

MIDI and Audio Group

(1)

Name

Pin Count

Type

Function

MIDI1_IN

1

IN

Main MIDI input. Routed to PDSP#1, can also be routed to PDSP#2.

MIDI2_IN

1

I/O

MIDI1_OUT

1

OUT

Main MIDI output. Outputs from PDSP#1.

MIDI2_OUT

1

OUT

OVCK_OUT

1

OUT

Buffered X2 output. Typically used to drive external sigma/delta DAC/ADC at

BCK_OUT

1

OUT

Audio data bit clock. Provides timing to SD_OUT.

WS_OUT

1

OUT

Audio data word select. WS_OUT timing can be selected to be I2S- or

Japanese-compatible.

SD_OUT[7:0]

8

OUT

8 stereo serial audio data output (16 audio channels). Each output holds 64 bits

SD_IN[7:0]

8

I/O

8 stereo serial audio data input (16 audio channels). Each input holds 64 bits

(2 x 32) of serial data per frame. Audio data in is received with 20-bit

Table 3-4.

Name

Pin Count

Type

Function

CK_OUT

1

OUT

Master clock for SDRAM operation. Frequency is 4 times the X1 frequency

(typ 45.1584 MHz).

WA[26:0]

27

OUT

External memory address (ROM/SRAM/DRAM/SDRAM), up to 128M words

(256M bytes).

DRAM/SDRAM addresses are time-multiplexed on these pins as follows:

WA0 - WA8: DRA0 - DRA8

WA18: DRA9

WA20: DRA10

WA22: DRA11

RBS

1

OUT

SRAM byte select. Should be connected to the lower RAM address when 8-bit

wide SRAM is used. The type of RAM (16-bit/8-bit) can be selected by

program.

WD[15:0]

16

I/O

PCM ROM/SRAM/DRAM/SDRAM data

WCS0

1

OUT

PCM ROM chip select, active low

WCS1

1

OUT

SRAM chip select, active low

WWE

1OUT

SRAM/DRAM/SDRAM write enable, active low. Timing compatible with SIMM

DRAM early write feature.

WOE

1

OUT

PCM ROM/SRAM output enable, active low