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ATSAM9708 数据表(PDF) 21 Page - ATMEL Corporation |
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ATSAM9708 数据表(HTML) 21 Page - ATMEL Corporation |
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21 / 31 page ![]() 21 1772E–DRMSD–10-Apr-06 ATSAM9708 Figure 15-3. 8-bit SRAM Read Cycle t WC Write cycle time 6 x t CK ns t CSWE Write enable low from CS t CK - 10 ns tOEWE Write enable low from Address or WOE 2tCK - 10 ns t WP Write pulse-width 3.5 x t CK ns tDW Data out setup time 3.5 x tCK - 10 ns tDH Data out hold time 0.5 x tCK ns Table 15-1. External 16-bit SRAM Timing Parameters (Continued) Symbol Parameter Min Typ Max Unit tRC tCSOE tPOE tOE tACE tDF WA[26:0] WD[7:0] WCS1 WOE WWE tORB tACH LOW HIGH RBS |
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