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1772E–DRMSD–10-Apr-06

ATSAM9708

• Both Synthesis/DSP enter an idle state.

•If REFRESH is low, then both P16 program execution starts from address 0100H in ROM

space (WCS0 low).

•If REFRESH is high, then both P16 program execution starts from address 0000H in

internal bootstrap ROM space. Each internal bootstrap expects to receive 256 words from

its respective 16-bit burst transfer port, which will be stored from 0100H to 01FFH into the

external DRAM space. The bootstrap then resumes control at address 0100H.

•If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal oscillator

and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power

down, PDWN has to be asserted high, then RESET applied.

22. Memory Type Configuration and Boot Configuration

At the end of power-up, when RESET input goes from low to high, RAS, CAS and REFRESH

pins are sampled by the ATSAM9708 to determine memory type configuration and boot type.

RAS, CAS and REFRESH must be pulled to V

select these different power-up configurations.

One memory type can be used for low pages (addresses [0-8000000h], AD[27] = 0) and a dif-

ferent type for high pages (addresses [8000000h-10000000h]).

Memory types allowed are Flash/ROM, SRAM, DRAM or SDRAM.

When using RAM (SRAM, DRAM or SDRAM) in low page, P16 must start in bootstrap state.

When in bootstrap state, P16 program execution starts at address 0. If not in bootstrap, pro-

gram execution starts at address 100h. Bootstrap is selected via the REFRESH pin.

Note:

1. When accessing DRAM or SDRAM, DRAM/SDRAM is selected by signals RAS and CAS (WCS0 and WCS1 are inactive)

and addresses are time-multiplexed on WA[..] pins as follows:

• WA0 - WA8: DRA0 - DRA8

• WA18: DRA9

• WA20: DRA10

• WA22: DRA11

When accessing SRAM, Flash or ROM, SRAM/Flash/ROM are selected by signals WCS0, WCS1 (RAS and CAS are inac-

tive) and WA[26:0] address pins:

• if low pages: WCS0 = 0, WCS1 = 1

• if high pages: WCS0 = 1, WCS1 = 0

Table 22-1.

Memory Type and Boot Configuration

Pin Level Detected at Reset

Low Page

High Page

REFRESH

RAS

CAS

Memory Type

Selected by

Memory Type

Selected by

Stand-alone Mode

Low

Low

Low

Flash/ROM

WCS0

SRAM

WCS1

Low

Low

High

Flash/ROM

WCS0

DRAM

RAS, CAS

Low

High

Low

Flash/ROM

WCS0

SDRAM

RAS, CAS

Low

High

High

Flash/ROM

WCS0

Selected by firmware

Bootstrap Mode

High

Low

Low

SRAM

WCS0

Flash/ROM

WCS1

High

Low

High

DRAM

RAS, CAS

Flash/ROM

WCS1

High

High

Low

SDRAM

RAS, CAS

Flash/ROM

WCS1