5

1772E–DRMSD–10-Apr-06

ATSAM9708

Note:

Note:

1. X2 cannot be used to drive external circuitry.

RAS

1

I/O

DRAM/SDRAM row address strobe. At the end of reset RAS is tested to

determine memory type configuration (pulled high to select SDRAM type). RAS

CAS

1

I/O

DRAM/SDRAM column address strobe. At the end of reset CAS is tested to

determine memory type configuration (pulled high to select DRAM type). CAS

REFRESH

1

I/O

Indicates that a DRAM/SDRAM memory refresh cycle is in progress. To be

used with multiple SIMM/DIMM modules to force refresh simultaneously on all

modules. At the end of reset REFRESH is tested to select bootstrap state

(pulled high to start built-in CPU bootstrap in case of ROMless applications).

Table 3-4.

Memory Group

Name

Pin Count

Type

Function

Table 3-5.

Miscellaneous Group

Name

Pin Count

Type

Function

LFT

1

ANA

PLL low pass filter. Should be connected to an external RC network.

TEST

1

IN

Test pin. Should be returned to GND.

LDTEST

1

IN

Test pin. Should be returned to GND.

PDWN

1

IN

Power down, active low

RESET

1

IN

Master reset input, active low. Schmidt trigger input.

2–

Crystal frequency is internally multiplied by 4 to provide the IC master clock. X1

can also be used as external clock input (3.3V input).