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数据搜索系统，热门电子元器件搜索 |
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ATSAM9708 数据表(PDF) 22 Page - ATMEL Corporation |
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ATSAM9708 数据表(HTML) 22 Page - ATMEL Corporation |
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22 / 31 page  22 1772E–DRMSD–10-Apr-06 ATSAM9708 Figure 15-4. 8-bit SRAM Write Cycle tWC tCSWE tWP WA[26:0] WD[7:0] WCS1 WOE WWE LOW HIGH RBS tWP tAS tDW1 tDH1 tDW2 tDH2 Table 15-2. External 8-bit SRAM Timing Parameters Symbol Parameter Min Typ Max Unit t RC Word (2 x bytes) read cycle time 6 x t CK ns tCSOE Chip select low/address valid to WOE low tCK ns t POE Output enable pulse width 5 x t CK ns t ACE Chip select/address low byte access time 3 x t CK - 5 ns tOE Output enable low byte access time 2 x tCK - 5 ns t ORB Output enable low to byte select high 2 x t CK ns t ACH Byte select high byte access time 3 x t CK - 5 ns t DF Chip select or WOE high to input data High Z 0t CK - 5 ns t WC Word (2 x bytes) write cycle time 6 x t CK ns tCSWE 1st WWE low from CS or Address or WOE tck - 10 ns t WP Write (low and high byte) pulse width 1.5 x t CK ns t DW1 Data out low byte setup time 1.5 x t CK - 10 ns tDH1 Data out low byte hold time 10 ns t AS RBS high to second write pulse t CK - 5 ns t DW2 Data out high byte setup time 2.5 x t CK - 10 ns tDH2 Data out high byte hold time 10 ns |
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