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ATSAM9708 数据表(PDF) 20 Page - ATMEL Corporation |
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ATSAM9708 数据表(HTML) 20 Page - ATMEL Corporation |
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20 / 31 page ![]() 20 1772E–DRMSD–10-Apr-06 ATSAM9708 15. External RAM Timing Figure 15-1. 16-bit SRAM Read Cycle Figure 15-2. 16-bit SRAM Write Cycle Table 15-1. External 16-bit SRAM Timing Parameters Symbol Parameter Min Typ Max Unit tRC Read cycle time 6 x tCK ns t AOE Address valid to WOE low t CK ns tPOE Output enable pulse width 5 x tCK ns t AD Address access time 6 x t CK - 5 ns t OE Output enable access time 5 x t CK - 5 ns tDF Chip select or WOE high to input data High Z 0 tCK - 5 ns tRC tAOE tPOE tOE tAD tDF WA[26:0] WD[15:0] WCS1 WOE WWE tWC tCSWE tWP tDW tDH WA[26:0] WD[15:0] WCS1 WOE WWE tOEWE |
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