AT89C51AC3-RDTIM datasheet(115/140 Pages) ATMEL

115 / 140 page

115

AT89C51AC3

4383D–8051–02/08

Registers

Table 65. IEN0 Register

IEN0 (S:A8h)

Interrupt Enable Register

Reset Value = 0000 0000b

bit addressable

ET2

ET1

EX1

ET0

EX0

Bit

Number

Bit

Mnemonic Description

Enable All Interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

PCA Interrupt Enable

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

ET2

Timer 2 Overflow Interrupt Enable bit

Clear to disable Timer 2 overflow interrupt.

Set to enable Timer 2 overflow interrupt.

Serial Port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

ET1

Timer 1 Overflow Interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

EX1

External Interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

ET0

Timer 0 Overflow Interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

EX0

External Interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

AT89C51AC3-RDTIM 数据表(PDF) 115 Page - ATMEL Corporation

AT89C51AC3-RDTIM 数据表(HTML) 115 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载