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AT89C51AC3-RDTIM 数据表(PDF) 111 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM 数据表(HTML) 111 Page - ATMEL Corporation |
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111 / 140 page  111 AT89C51AC3 4383D–8051–02/08 Table 60. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Reset Value = XXX0 0000b Note: 1. In X1 mode: For PRS > 0 F ADC = FXTAL 4xPRS For PRS = 0 FADC = FXTAL 128 In X2 mode: For PRS > 0 FADC = FXTAL 2xPRS For PRS = 0 F ADC = FXTAL 64 Table 61. ADDH Register ADDH (S:F5h Read Only) ADC Data High Byte Register Reset Value = 00h Table 62. ADDL Register ADDL (S:F4h Read Only) ADC Data Low Byte Register 7 6 5 4 3 2 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic Description 7-5 - Reserved The value read from these bits are indeterminate. Do not set these bits. 4-0 PRS4:0 Clock Prescaler See Note (1) 7 6 5 4 3 2 1 0 ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2 Bit Number Bit Mnemonic Description 7-0 ADAT9:2 ADC result bits 9-2 7 6 5 4 3 2 1 0 - - - - - - ADAT 1 ADAT 0 |
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