AT89C51AC3-RDTIM datasheet(110/140 Pages) ATMEL

110 / 140 page

110

AT89C51AC3

4383D–8051–02/08

Registers

Table 58. ADCF Register

ADCF (S:F6h)

ADC Configuration

Reset Value =0000 0000b

Table 59. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset Value =X000 0000b

CH 7

CH 6

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Bit

Number

Bit

Mnemonic Description

7-0

CH 0:7

Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit

Number

Bit

Mnemonic Description

PSIDLE

Pseudo Idle Mode (Best Precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

ADEN

Enable/Standby Mode

Set to enable ADC

Clear for Standby mode (power dissipation 1 uW).

ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

ADSST

Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0

SCH2:0

Selection of Channel to Convert

see Table 57

AT89C51AC3-RDTIM 数据表(PDF) 110 Page - ATMEL Corporation

AT89C51AC3-RDTIM 数据表(HTML) 110 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载