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AT89C51AC3-RDTIM 数据表(PDF) 106 Page - ATMEL Corporation |
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AT89C51AC3-RDTIM 数据表(HTML) 106 Page - ATMEL Corporation |
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106 / 140 page  106 AT89C51AC3 4383D–8051–02/08 Figure 59. ADC Description Figure 60 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the AT89C51AC3 datasheet. Figure 60. Timing Diagram Note: Tsetup min = 4 us Tconv=11 clock ADC = 1sample and hold + 10 bit conversion The user must ensure that 4 us minimum time between setting ADEN and the start of the first conversion. AN0/P1.0 AN1/P1.1 AN2/P1.2 AN3/P1.3 AN4/P1.4 AN5/P1.5 AN6/P1.6 AN7/P1.7 000 001 010 011 100 101 110 111 SCH2 ADCON.2 SCH0 ADCON.0 SCH1 ADCON.1 ADC CLOCK ADEN ADCON.5 ADSST ADCON.3 ADEOC ADCON.4 ADC Interrupt Request EADC IEN1.1 CONTROL AVSS Sample and Hold ADDH VAREF R/2R DAC VAGND 8 10 + - ADDL 2 SAR ADCIN ADEN ADSST ADEOC T SETUP T CONV CLK |
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