AT89C51AC3-RDTIM datasheet(107/140 Pages) ATMEL

107 / 140 page

107

AT89C51AC3

4383D–8051–02/08

ADC Converter

Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an interrupt occur when flag ADEOC is set (see Figure 62). Clear this flag for re-

arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

Table 57. Selected Analog input

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (See section

“AC-DC”)

Clock Selection

The ADC clock is the same as CPU.

The maximum clock frequency is defined in the DC parmeters for A/D converter. A pres-

caler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency.

fADC = fcpu clock/ (4 (or 2 in X2 mode)* PRS )

if PRS > 0 then fADC = Fperiph / 2 x PRS

if PRS = 0 then fADC = Fperiph / 64

SCH2

SCH1

SCH0

Selected Analog input

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AT89C51AC3-RDTIM 数据表(PDF) 107 Page - ATMEL Corporation

AT89C51AC3-RDTIM 数据表(HTML) 107 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载