AT89C51ED2-RDTUM datasheet(67/137 Pages) ATMEL

67 / 137 page

4235K–8051–05/08

AT89C51RD2/ED2

Figure 16-4. Data Transmission Format (CPHA = 0)

Figure 16-5. Data Transmission Format (CPHA = 1)

Figure 16-6. CPHA/SS Timing

As shown in Figure 16-4, the first SCK edge is the MSB capture strobe. Therefore, the Slave

must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to

start the transmission. The SS pin must be toggled high and then low between each Byte trans-

mitted (Figure 16-6).

Figure 16-5 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins

driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a

start transmission signal. The SS pin can remain low between transmissions (Figure 16-6). This

format may be preferred in systems having only one Master and only one Slave driving the

MISO data line.

16.3.3

Error Conditions

The following flags in the SPSTA signal SPI error conditions:

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

bit6

bit5

bit4

bit3

bit2

bit1

MSB

LSB

Capture Point

SS (to Slave)

MISO (from Slave)

MOSI (from Master)

SCK (CPOL = 1)

SCK (CPOL = 0)

SPEN (Internal)

SCK Cycle Number

Byte 1

Byte 2

Byte 3

MISO/MOSI

Master SS

Slave SS

(CPHA = 1)

Slave SS

(CPHA = 0)

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