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AT89C51ED2-RDTUM 数据表(PDF) 78 Page - ATMEL Corporation |
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AT89C51ED2-RDTUM 数据表(HTML) 78 Page - ATMEL Corporation |
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78 / 137 page  78 4235K–8051–05/08 AT89C51RD2/ED2 Table 17-7. IPL1 Register IPL1 - Interrupt Priority Register (B2h) Reset Value = XXXX X000b Bit addressable 7 6 5 4 3 2 1 0 - - - - - SPIL TWIL KBDL Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 SPIL SPI interrupt Priority bit Refer to SPIH for priority level. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 KBDL Keyboard interrupt Priority bit Refer to KBDH for priority level. |
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