AT89C51ED2-RDTUM datasheet(70/137 Pages) ATMEL

70 / 137 page

4235K–8051–05/08

AT89C51RD2/ED2

Reset Value = 0001 0100b

Not bit addressable

16.3.5.2

Serial Peripheral Status Register (SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

• Data transfer complete

• Write collision

• Inconsistent logic level on SS pin (mode fault error)

Table 16-4 describes the SPSTA register and explains the use of every bit in the register.

Table 16-4.

SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

MSTR

Serial Peripheral Master

Cleared to configure the SPI as a Slave.

Set to configure the SPI as a Master.

CPOL

Clock Polarity

Cleared to have the SCK set to ’0’ in idle state.

Set to have the SCK set to ’1’ in idle low.

CPHA

Clock Phase

Cleared to have the data sampled when the SCK leaves the idle state (see

CPOL).

Set to have the data sampled when the SCK returns to idle state (see

CPOL).

SPR1

SPR2 SPR1 SPR0 Serial Peripheral Rate

CLK PERIPH /2

CLK PERIPH /4

0 F

CLK PERIPH /8

CLK PERIPH /16

CLK PERIPH /32

CLK PERIPH /64

CLK PERIPH /128

1Invalid

SPR0

Bit Number

Bit Mnemonic

Description

SPIF

WCOL

SSERR

MODF

Bit Number

Bit

Mnemonic

Description

SPIF

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been approved by a

clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

WCOL

Write Collision Flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a

clearing sequence.

Set by hardware to indicate that a collision has been detected.

AT89C51ED2-RDTUM 数据表(PDF) 70 Page - ATMEL Corporation

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