AT89C51ED2-RDTUM datasheet(83/137 Pages) ATMEL

83 / 137 page

4235K–8051–05/08

AT89C51RD2/ED2

18.4

Registers

Table 18-2.

PCON Register

PCON (S87:h) Power configuration Register

Reset Value= XXXX 0000b

GF1

GF0

IDL

Bit Number

Bit

Mnemonic

Description

7-4

Reserved

The value read from these bits is indeterminate. Do not set these bits.

GF1

General Purpose flag 1

One use is to indicate whether an interrupt occurred during normal operation or during

Idle mode.

GF0

General Purpose flag 0

One use is to indicate whether an interrupt occurred during normal operation or during

Idle mode.

Power-Down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-Down mode.

If IDL and PD are both set, PD takes precedence.

IDL

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

If IDL and PD are both set, PD takes precedence.

AT89C51ED2-RDTUM 数据表(PDF) 83 Page - ATMEL Corporation

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