AT89C51ED2-RDTUM datasheet(33/137 Pages) ATMEL

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4235K–8051–05/08

AT89C51RD2/ED2

Reset Value = 0000 0000b

Bit addressable

Bit

Number

Bit

Mnemonic

Description

TF2

Timer 2 overflow Flag

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2

= 1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2 interrupt

is enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode

(DCEN = 1).

RCLK

Receive Clock bit

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

TCLK

Transmit Clock bit

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

EXEN2

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if

Timer 2 is not used to clock the serial port.

TR2

Timer 2 Run control bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

C/T2#

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: F

CLK PERIPH).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for

clock out mode.

CP/RL2#

Timer 2 Capture/Reload bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload on Timer

2 overflow.

Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

AT89C51ED2-RDTUM 数据表(PDF) 33 Page - ATMEL Corporation

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