9202 datasheet(65/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

DATA is activated, which enables the output bit of

the transmit shift register to TxD. The first shift

pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked

in from the left. When the MSB of the data byte is

at the output position of the shift register, then the

'1' that was initially loaded into the 9th position is

just to the left of the MSB, and all positions to the

left of that contain zeros. This condition flags the

TX Control unit to do one last shift and then deac-

tivate SEND and set TI. This occurs at the 10th di-

vide-by-16 rollover after “WRITE to SBUF.”

Reception is initiated by a detected 1-to-0 transi-

tion at RxD. For this purpose RxD is sampled at a

rate of 16 times whatever baud rate has been es-

tablished. When a transition is detected, the di-

vide-by-16 counter is immediately reset, and 1FFH

is written into the input shift register. Resetting the

divide-by-16 counter aligns its roll-overs with the

boundaries of the incoming bit times.

The 16 states of the counter divide each bit time

into 16ths. At the 7th, 8th, and 9th counter states

of each bit time, the bit detector samples the value

of RxD. The value accepted is the value that was

seen in at least 2 of the 3 samples. This is done for

noise rejection. If the value accepted during the

first bit time is not '0,' the receive circuits are reset

and the unit goes back to looking for an-other 1-to-

0 transition. This is to provide rejection of false

start bits. If the start bit proves valid, it is shifted

into the input shift register, and reception of the re-

set of the rest of the frame will proceed.

As data bits come in from the right, '1s' shift out to

the left. When the start bit arrives at the left-most

position in the shift register (which in Mode 1 is a

9-bit register), it flags the RX Control block to do

one last shift, load SBUF and RB8, and set RI. The

signal to load SBUF and RB8, and to set RI, will be

generated if, and only if, the following conditions

are met at the time the final shift pulse is generat-

ed:

1. R1 = 0, and

2. Either SM2 = 0, or the received Stop Bit = 1.

If either of these two conditions is not met, the re-

ceived frame is irretrievably lost. If both conditions

are met, the Stop Bit goes into RB8, the 8 data bits

go into SBUF, and RI is activated. At this time,

whether the above conditions are met or not, the

unit goes back to looking for a 1-to-0 transition in

RxD.

More About Modes 2 and 3. Eleven

bits

are

transmitted (through TxD), or received (through

RxD): a Start Bit (0), 8 data bits (LSB first), a pro-

grammable 9th data bit, and a Stop Bit (1). On

transmit, the 9th data bit (TB8) can be assigned

the value of '0' or '1.' On receive, the data bit goes

into RB8 in SCON. The baud rate is programma-

ble to either 1/16 or 1/32 the CPU clock frequency

in Mode 2. Mode 3 may have a variable baud rate

generated from Timer 1.

Figure 31, page 68 and Figure 33, page 69 show

a functional diagram of the serial port in Modes 2

and 3. The receive portion is exactly the same as

in Mode 1. The transmit portion differs from Mode

1 only in the 9th bit of the transmit shift register.

Transmission is initiated by any instruction that

uses SBUF as a destination register. The “WRITE

to SBUF” signal also loads TB8 into the 9th bit po-

sition of the transmit shift register and flags the TX

Control unit that a transmission is requested.

Transmission commences at S1P1 of the machine

cycle following the next roll-over in the divide-by-

16 counter. (Thus, the bit times are synchronized

to the divide-by-16 counter, not to the “WRITE to

SBUF” signal.)

The transmission begins with activation of SEND,

which puts the start bit at TxD. One bit time later,

DATA is activated, which enables the output bit of

the transmit shift register to TxD. The first shift

pulse occurs one bit time after that. The first shift

clocks a '1' (the Stop Bit) into the 9th bit position of

the shift register. There-after, only zeros are

clocked in. Thus, as data bits shift out to the right,

zeros are clocked in from the left. When TB8 is at

the out-put position of the shift register, then the

Stop Bit is just to the left of TB8, and all positions

to the left of that contain zeros. This condition flags

the TX Control unit to do one last shift and then de-

activate SEND and set TI. This occurs at the 11th

divide-by 16 rollover after “WRITE to SUBF.”

Reception is initiated by a detected 1-to-0 transi-

tion at RxD. For this purpose RxD is sampled at a

rate of 16 times whatever baud rate has been es-

tablished. When a transition is detected, the di-

vide-by-16 counter is immediately reset, and 1FFH

is written to the input shift register.

At the 7th, 8th, and 9th counter states of each bit

time, the bit detector samples the value of R-D.

The value accepted is the value that was seen in

at least 2 of the 3 samples. If the value accepted

during the first bit time is not '0,' the receive circuits

are reset and the unit goes back to looking for an-

other 1-to-0 transition. If the Start Bit proves valid,

it is shifted into the input shift register, and recep-

tion of the rest of the frame will proceed.

As data bits come in from the right, '1s' shift out to

the left. When the Start Bit arrives at the left-most

position in the shift register (which in Modes 2 and

3 is a 9-bit register), it flags the RX Control block

to do one last shift, load SBUF and RB8, and set

RI.

The signal to load SBUF and RB8, and to set RI,

will be generated if, and only if, the following con-

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