9202 datasheet(82/175 Pages) STMICROELECTRONICS

82 / 175 page

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

82/175

DDC INTERFACE

The basic DDC unit consists of an I2C interface

and 256 bytes of SRAM for DDC data storage. The

8032 core is responsible of loading the contents of

the SRAM with the DDC data. The DDC unit has

the following features:

Supports both DDC1 and DDC2b Modes.

Features 256 bytes of DDC data - initialized by

the 8032

Supports fully automatic operation of DDC1 and

DDC2b Modes

DDC operates in Slave Mode only.

SW Interrupt Mode available (existing design)

The interface signals for the DDC can be mapped

to pins in Port 4. The interface consists of the stan-

dard VSYNC (P4.2), SDA (P4.0) and SCL (P4.1)

DDC signals. The conceptual block diagram is il-

lustrated in Figure 43.

Figure 40. DDC Interface Block Diagram

AI06628

INT

DDCCON

INTR (from SISTA)

Initialization Synchronization

DDCADR

Address Pointer

RAM

Buffer

RAMBUF

VSYNCEN

DDC1 Transmitter

DDCDAT

DDC1 Hold Register

DDC1/DDC2

Detection

SISTA

SICON

SCL1

SDA1

Bus Clock Generator

Arbitration Logic

S1DAT

S1ADR1

S1ADR0

Shift Register

DDC2B/DDC2AB

DDC2B+Interface

Monitor Address

EX_

DAT

ENB

DDC1

INT

DDC1

SWH

INT

9202 数据表(PDF) 82 Page - STMicroelectronics

9202 数据表(HTML) 82 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载