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9202 数据表(PDF) 55 Page - STMicroelectronics |
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9202 数据表(HTML) 55 Page - STMicroelectronics |
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55 / 175 page ![]() 55/175 UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV Mode 0. Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 22 shows the Mode 0 operation as it applies to Timer 1. In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all '1s' to all '0s,' it sets the Timer Interrupt Flag TF1. The counted input is enabled to the Timer when TR1 = 1 and either GATE = 0 or /INT1 = 1. (Setting GATE = 1 allows the Timer to be controlled by external in- put /INT1, to facilitate pulse width measurements). TR1 is a control bit in the Special Function Regis- ter TCON (TCON Control Register). GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag does not clear the registers. Mode 0 operation is the same for the Timer 0 as for Timer 1. Substitute TR0, TF0, and /INT0 for the corresponding Timer 1 signals in Figure 22. There are two different GATE Bits, one for Timer 1 and one for Timer0. Mode 1. Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits. Table 38. TMOD Register (TMOD) Table 39. Description of the TMOD Bits 76 543210 Gate C/T M1 M0 Gate C/T M1 M0 Bit Symbol Timer Function 7Gate Timer1 Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set 6C/T Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T1 input pin) 5 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1 each time it overflows (M1,M0)=(1,1): Timer/Counter 1 stopped 4M0 3Gate Timer0 Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 control bit is set 2C/T Timer or Counter selector, cleared for timer operation (input from internal system clock); set for counter operation (input from T0 input pin) 1 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler (M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler. (M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be reloaded into TL0 each time it overflows (M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits 0M0 |
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