9202 datasheet(79/175 Pages) STMICROELECTRONICS

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UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

Table 50. Serial Control Register (SxCON: S1CON, S2CON)

Table 51. Description of the SxCON Bits

Table 52. Selection of the Serial Clock Frequency SCL in Master Mode

543210

CR2

ENII

STA

STO

ADDR

CR1

CR0

Bit

Symbol

Function

7CR2

This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is

in the Master Mode.

6ENII

Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high

impedance state.

5STA

START flag. When this bit is set, the SIO H/W checks the status of the I2C-bus and

generates a START condition if the bus free. If the bus is busy, the SIO will generate a

repeated START condition when this bit is set.

4STO

STOP flag. With this bit set while in Master Mode a STOP condition is generated.

When a STOP condition is detected on the I2C-bus, the I2C hardware clears the STO

flag.

Note: This bit have to be set before 1 cycle interrupt period of STOP. That is, if this bit is

set, STOP condition in Master Mode is generated after 1 cycle interrupt period.

ADDR

This bit is set when address byte was received. Must be cleared by software.

2AA

Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is

returned during the acknowledge clock pulse on the SCL line when:

• Own slave address is received

• A data byte is received while the device is programmed to be a Master Receiver

• A data byte is received while the device is a selected Slave Receiver. When this bit is

reset, no acknowledge is returned.

SIO release SDA line as high during the acknowledge clock pulse.

1CR1

These two bits along with the CR2 Bit determine the serial clock frequency when SIO is

in the Master Mode.

0CR0

CR2

CR1

CR0

fOSC Divisor

Bit Rate (kHz) at fOSC

12MHz

24MHz

36MHz

40MHz

375

750

250

500

750

833

200

400

600

666

100

200

300

333

120

100

150

166

240

480

12.5

37.5

960

6.25

12.5

18.75

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