9202 datasheet(94/175 Pages) STMICROELECTRONICS

94 / 175 page

UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV

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Table 73. USB Control Register (UCON2: 0ECh)

Table 74. Description of the UCON2 Bits

Table 75. USB Endpoint0 Status Register (USTA: 0EDh)

Table 76. Description of the USTA Bits

Table 77. USB Endpoint0 Data Receive Register (UDR0: 0EFh)

Table 78. USB Endpoint0 Data Transmit Register (UDT0: 0E7h)

Table 79. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)

543210

—

SOUT

EP2E

EP1E

STALL2

STALL1

Bit

Symbol

R/W

Function

7 to 5

—

Reserved

SOUT

R/W

Status out is used to automatically respond to the OUT of a control READ

transfer

EP2E

R/W

Endpoint2 enable. RESET clears this bit

EP1E

R/W

Endpoint1 enable. RESET clears this bit

STALL2

R/W

Endpoint2 Force Stall Bit. RESET clears this bit

STALL1

R/W

Endpoint1 Force Stall Bit. RESET clears this bit

543210

RSEQ

SETUP

OUT

RP0SIZ3

RP0SIZ2

RP0SIZ1

RP0SIZ0

Bit

Symbol

R/W

Function

RSEQ

R/W

Endpoint0 receive data packet PID. (0=DATA0, 1=DATA1)

This bit will be compared with the type of data packet last received for

Endpoint0

SETUP

SETUP Token Detect Bit. This bit is set when the received token packet

is a SEPUP token, PID = b1101.

5IN

IN Token Detect Bit.

This bit is set when the received token packet is an IN token.

4OUT

OUT Token Detect Bit.

This bit is set when the received token packet is an OUT token.

3 to 0

RP0SIZ3 to

RP0SIZ0

The number of data bytes received in a DATA packet

76543210

UDR0.7

UDR0.6

UDR0.5

UDR0.4

UDR0.3

UDR0.2

UDR0.1

UDR0.0

76543210

UDT0.7

UDT0.6

UDT0.5

UDT0.4

UDT0.3

UDT0.2

UDT0.1

UDT0.0

76543210

UDT1.7

UDT1.6

UDT1.5

UDT1.4

UDT1.3

UDT1.2

UDT1.1

UDT1.0

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