A14100A-RQ208C datasheet(8/68 Pages) ACTEL

8 / 68 page

1-182

The S-module contains a full implementation of the C-module

plus a clearable sequential element that can either

implement a latch or flip-flop function. The S-module can

therefore implement any function implemented by the

C-module. This allows complex combinatorial-sequential

functions to be implemented with no delay penalty. The

Designer Series Development System will automatically

combine any C-module macro driving an S-module macro into

the S-module, thereby freeing up a logic module and

eliminating a module delay.

The clear input CLR is accessible from the routing channel.

In addition, the clock input may be connected to one of three

clock networks: CLKA, CLKB, or HCLK. The C-module and

S-module functional descriptions are shown in Figures 2

and 3. The clock selection is determined by a multiplexor

select at the clock input to the S-module.

I/Os

I/O Modules

I/O modules provide an interface between the array and the

I/O Pad Drivers. I/O modules are located in the array and

access the routing channels in a similar fashion to logic

modules. The I/O module schematic is shown in Figure 4. The

signals DataIn and DataOut connect to the I/O pad driver.

Each I/O module contains two D-type flip-flops. Each flip-flop

is connected to the dedicated I/O clock (IOCLK). Each

flip-flop can be bypassed by nonsequential I/Os. In addition,

each flip-flop contains a data enable input that can be

accessed from the routing channels (ODE and IDE). The

asynchronous preset/clear input is driven by the dedicated

preset/clear network (IOPCL). Either preset or clear can be

selected individually on an I/O module by I/O module basis.

The I/O module output Y is used to bring Pad signals into the

array or to feed the output register back into the array. This

allows the output register to be used in high-speed state

machine applications. Side I/O modules have a dedicated

output segment for Y extending into the routing channels

above and below (similar to logic modules). Top/Bottom I/O

modules have no dedicated output segment. Signals coming

into the chip from the top or bottom are routed using F-fuses

and LVTs (F-fuses and LVTs are explained in detail in the

routing section).

Figure 2 • C-Module Diagram

D11

D01

D00

D10

A1 B1

A0 B0

OUT

Figure 3 • S-Module Diagram

CLR

CLK

D11

D01

D00

D10

A1 B1

A0 B0

OUT

A14100A-RQ208C 数据表(PDF) 8 Page - Actel Corporation

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