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A14100A-RQ208C 数据表(PDF) 32 Page - Actel Corporation

部件名 A14100A-RQ208C
功能描述  Accelerator Series FPGAs - ACT 3Family
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ACTEL [Actel Corporation]
网页  http://www.actel.com
标志 ACTEL - Actel Corporation

A14100A-RQ208C 数据表(HTML) 32 Page - Actel Corporation

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A1425A, A14V25A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Note:
1.
Delays based on 35pF loading.
Dedicated (Hard-Wired) I/O Clock
Network
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
3.3V Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
tIOCKH
Input Low to High
(Pad to I/O Module Input)
2.0
2.3
2.6
3.0
3.5
ns
tIOPWH
Minimum Pulse Width High
1.9
2.4
3.3
3.8
4.8
ns
tIOPWL
Minimum Pulse Width Low
1.9
2.4
3.3
3.8
4.8
ns
tIOSAPW
Minimum Asynchronous
Pulse Width
1.9
2.4
3.3
3.8
4.8
ns
tIOCKSW
Maximum Skew
0.4
0.4
0.4
0.4
0.4
ns
tIOP
Minimum Period
4.0
5.0
6.8
8.0
10.0
ns
fIOMAX
Maximum Frequency
250
200
150
125
100
MHz
Dedicated (Hard-Wired) Array Clock
Network
tHCKH
Input Low to High
(Pad to S-Module Input)
3.0
3.4
3.9
4.5
5.5
ns
tHCKL
Input High to Low
(Pad to S-Module Input)
3.0
3.4
3.9
4.5
5.5
ns
tHPWH
Minimum Pulse Width High
1.9
2.4
3.3
3.8
4.8
ns
tHPWL
Minimum Pulse Width Low
1.9
2.4
3.3
3.8
4.8
ns
tHCKSW
Maximum Skew
0.3
0.3
0.3
0.3
0.3
ns
tHP
Minimum Period
4.0
5.0
6.8
8.0
10.0
ns
fHMAX
Maximum Frequency
250
200
150
125
100
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (FO=64)
3.7
4.1
4.7
5.5
9.0
ns
tRCKL
Input High to Low (FO=64)
4.0
4.5
5.1
6.0
9.0
ns
tRPWH
Min. Pulse Width High
(FO=64)
3.3
3.8
4.2
4.9
6.5
ns
tRPWL
Min. Pulse Width Low
(FO=64)
3.3
3.8
4.2
4.9
6.5
ns
tRCKSW
Maximum Skew (FO=128)
0.7
0.8
0.9
1.0
1.0
ns
tRP
Minimum Period (FO=64)
6.8
8.0
8.7
10.0
13.4
ns
fRMAX
Maximum Frequency
(FO=64)
150
125
115
100
75
MHz
Clock-to-Clock Skews
tIOHCKSW
I/O Clock to H-Clock Skew
0.0
1.7
0.0
1.8
0.0
2.0
0.0
2.2
0.0
3.0
ns
tIORCKSW
I/O Clock to R-Clock Skew
(FO = 64)
(FO = 80)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
3.0
3.0
ns
ns
tHRCKSW
H-Clock to R-Clock Skew
(FO = 64)
(FO = 80)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns



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