A14100A-RQ208C datasheet(18/68 Pages) ACTEL

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1-192

Fixed Capacitance Values for Actel FPGAs

(pF)

Fixed Clock Loads (s1/s2)

Determining Average Switching Frequency

To determine the switching frequency for a design, you must

have a detailed understanding of the data input values to the

circuit. The following guidelines are meant to represent

worst-case scenarios so that they can be generally used to

predict the upper limits of power dissipation. These

guidelines are as follows:

Device Type

routed_Clk1

routed_Clk2

A1415A

A14V15A

A1425A

A14V25A

A1440A

105

A14V40A

100

A1440B

105

A1460A

165

A14V60A

157

A1460B

165

A14100A

195

A14V100A

185

A14100B

195

Clock Loads on

Device Type

dedicated array

clock

dedicated I/O

clock

A1415A

104

A14V15A

104

A1425A

160

100

A14V25A

160

100

A1440A

288

140

A14V40A

288

140

A1440B

288

140

A1460A

432

168

A14V60A

432

168

A1460B

432

168

A14100A

697

228

A14V100A

697

228

A14100B

697

228

Logic Modules (m)

= 80% of modules

Inputs switching (n)

= # inputs/4

Outputs switching (p)

= # output/4

First routed array clock loads (q1)

= 40% of

sequential

modules

Second routed array clock loads (q2)

= 40% of

sequential

modules

Load capacitance (CL)

= 35 pF

Average logic module switching rate

(fm)

= F/10

Average input switching rate (fn)

= F/5

Average output switching rate (fp)

= F/10

Average first routed array clock rate

(fq1)

= F/2

Average second routed array clock rate

(fq2)

= F/2

Average dedicated array clock rate

(fs1)

= F

Average dedicated I/O clock rate (fs2) = F

A14100A-RQ208C 数据表(PDF) 18 Page - Actel Corporation

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