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A14100A-RQ208C 数据表(PDF) 21 Page - Actel Corporation |
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A14100A-RQ208C 数据表(HTML) 21 Page - Actel Corporation |
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21 / 68 page ![]() 1-195 Accelerator Series FPGAs – ACT ™ 3 Family Sequential Module Timing Characteristics Flip-Flops I/O Module: Sequential Input Timing Characteristics (Positive edge triggered) D CLK CLR Q D CLK Q CLR tWCLKA tWASYN tHD tSUD tA tWCLKA tCO tCLR (Positive edge triggered) D E IOCLK CLR PRE Y D IOCLK E Y PRE, CLR tIOPWH tIOASPW tINH tIDESU tINSU tICLRY tIOP tIOPWL tICKY tIDEH |
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