数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

A14100A-RQ208C 数据表(PDF) 29 Page - Actel Corporation

部件名 A14100A-RQ208C
功能描述  Accelerator Series FPGAs - ACT 3Family
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ACTEL [Actel Corporation]
网页  http://www.actel.com
标志 ACTEL - Actel Corporation

A14100A-RQ208C 数据表(HTML) 29 Page - Actel Corporation

Back Button A14100A-RQ208C Datasheet HTML 25Page - Actel Corporation A14100A-RQ208C Datasheet HTML 26Page - Actel Corporation A14100A-RQ208C Datasheet HTML 27Page - Actel Corporation A14100A-RQ208C Datasheet HTML 28Page - Actel Corporation A14100A-RQ208C Datasheet HTML 29Page - Actel Corporation A14100A-RQ208C Datasheet HTML 30Page - Actel Corporation A14100A-RQ208C Datasheet HTML 31Page - Actel Corporation A14100A-RQ208C Datasheet HTML 32Page - Actel Corporation A14100A-RQ208C Datasheet HTML 33Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 68 page
background image
1-203
Accelerator Series FPGAs – ACT ™ 3 Family
A1425A, A14V25A Timing Characteristics
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
1
Notes:
1.
VCC = 3.0 V for 3.3V specifications.
2.
For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
3.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
Logic Module Propagation Delays2
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed 3.3V Speed1
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
tPD
Internal Array Module
2.0
2.3
2.6
3.0
3.9
ns
tCO
Sequential Clock to Q
2.0
2.3
2.6
3.0
3.9
ns
tCLR
Asynchronous Clear to Q
2.0
2.3
2.6
3.0
3.9
ns
Predicted Routing Delays3
tRD1
FO=1 Routing Delay
0.9
1.0
1.1
1.3
1.7
ns
tRD2
FO=2 Routing Delay
1.2
1.4
1.6
1.8
2.4
ns
tRD3
FO=3 Routing Delay
1.4
1.6
1.8
2.1
2.8
ns
tRD4
FO=4 Routing Delay
1.7
1.9
2.2
2.5
3.3
ns
tRD8
FO=8 Routing Delay
2.8
3.2
3.6
4.2
5.5
ns
Logic Module Sequential Timing
tSUD
Flip-Flop Data Input Setup
0.5
0.6
0.7
0.8
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tSUD
Latch Data Input Setup
0.5
0.6
0.7
0.8
0.8
ns
tHD
Latch Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
1.9
2.4
3.2
3.8
4.8
ns
tWCLKA
Flip-Flop Clock Pulse Width
1.9
2.4
3.2
3.8
4.8
ns
tA
Flip-Flop Clock Input Period
4.0
5.0
6.8
8.0
10.0
ns
fMAX
Flip-Flop Clock Frequency
250
200
150
125
100
MHz



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com