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Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

HardCopy III Device Handbook, Volume 3

© December 2008

Altera Corporation

Switching Characteristics

This section provides performance characteristics of HardCopy III core and periphery

blocks for commercial grade devices. HardCopy III devices are designed to meet, at

minimum, the –3 speed grade of the Stratix III devices. Silicon characterization

determines the actual performance of the HardCopy III devices. These characteristics

can be designated as Preliminary or Final, as defined below.

■

Preliminary

—Preliminary characteristics are created using simulation results,

process data, and other known parameters.

■

Final

—Final numbers are based on actual silicon characterization and testing.

These numbers reflect the actual performance of the device under worst-case

silicon process, voltage, and junction temperature conditions.

Core Performance Specifications

This sections describes the clock tree, phase-locked loop (PLL), digital signal

processing (DSP), TriMatrix, configuration, and JTAG specifications.

Clock Tree Specifications

Table 1–18 lists clock tree performance specifications for the logic array, DSP blocks,

and TriMatrix Memory blocks for HardCopy III devices.

Table 1–18. HardCopy III Clock Tree Performance – Preliminary

(Note 1)

Device

Commercial Grade (MHz)

Unit

HC311

500

MHz

HC321

500

MHz

HC322

500

MHz

HC331

500

MHz

HC332

500

MHz

HC351

500

MHz

HC352

500

MHz

HC361

500

MHz

HC362

500

MHz

HC372

500

MHz

Note to Table 1–18:

(1) Pending silicon characterization.