1–22

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Glossary

HardCopy III Device Handbook, Volume 3

© December 2008

Altera Corporation

I

——

J

J

HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).

JTAG Timing

Specifications

Figure 1–3. JTAG Timing Specifications

K

——

L

——

M—

—

N—

—

O

——

P

PLL

Specifications

The block diagram shown in the following figure highlights the PLL Specification parameters:

Figure 1–4. Diagram of PLL Specifications (Note 1)

Note:

(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.

Q

——

R

R

L

Receiver differential input discrete resistor (external to HardCopy III device).

Table 1–33. Glossary Table

Letter

Subject

Definitions

TDO

TCK

TDI

TMS

Core Clock

External Feedback

Reconfigurable in User Mode

Key

CLK

N

M

PFD

Switchover

VCO

CP

LF

CLKOUT Pins

GCLK

RCLK

Counters

C0..C9