Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–17

Switching Characteristics

© December 2008

Altera Corporation

HardCopy III Device Handbook, Volume 3

High-Speed I/O Specifications

Refer to Table 1–33 for definitions of high-speed timing specifications.

Table 1–23 shows the high-speed I/O timing for HardCopy III devices.

Table 1–23. High Speed I/O Specifications – Preliminary

(Note 1), (2), (3)

Symbol

Conditions

Min

Typ

Max

Unit

f

Clock boost factor W = 2 to 32 (4)

5—

625

MHz

Clock boost factor W = 1 (SERDES bypassed)

5

—

600

MHz

Clock boost factor W = 1 (SERDES used)

150

—

717

MHz

Dedicate LVDS-f

rate)

SERDES factor J = 3 to 10

150

—

1250

Mbps

SERDES factor J = 2, uses DDR registers

—

—

TBD (5)

Mbps

SERDES factor J = 1, uses SDR register

—

—

TBD (5)

Mbps

Dedicated LVDS-f

rate)

—

150

—

1250

Mbps

LVDS_E_3R-f

HSDR

—

—

—

340

Mbps

LVDS_E_1R-f

—

—

—

200

Mbps

Transmitter

t

Total jitter for data rate, 600 Mbps - 1.25 Gbps

—

—

160

ps

Total jitter for data rate, < 600 Mbps

—

—

0.1

UI

Dedicated LVDS Output t

RISE

and t

FALL

All differential I/O standards

—

—

200

ps

t

DUTY

TX output clock duty cycle

45

50

55

%

TCCS

All differential I/O standards

—

—

100

ps

DPA mode

DPA run length

—

—

—

(5)

UI

Soft CDR mode

Soft CDR jitter tolerance

—

—

—

(5)

ps

Soft CDR run length

—

—

—

(5)

UI

Soft-CDR PPM tolerance

—

—

—

(5)

PPM

Non DPA mode

Sampling window

All differential I/O standards

—

—

(5)

ps

Notes to Table 1–23:

(1) When J = 3 to 10, the serializer/deserializer (SERDES) block is used.

(2) When J = 1 or 2, the SERDES block is bypassed.

(3) The minimum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional,

or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.

(4) The input clock frequency and the W factor must satisfy the following Left and Right PLL output frequency specification: 150 MHz input clock

frequency × W

≤ 1250 MHz.

(5) Pending silicon characterization.