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HC331 数据表(PDF) 25 Page - Altera Corporation

部件名 HC331
功能描述  HardCopy III Device
PDF  26 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

HC331 数据表(HTML) 25 Page - Altera Corporation

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Chapter 1: DC and Switching Characteristics of HardCopy III Devices
1–23
Glossary
© December 2008
Altera Corporation
HardCopy III Device Handbook, Volume 3
S
SW (sampling
window)
The period of time during which the data must be valid in order to capture it correctly. The
setup and hold times determine the ideal strobe position within the sampling window.
Figure 1–5. Timing Diagram
Single-ended
Voltage
Referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input
signal values. The AC values indicate the voltage levels at which the receiver must meet its
timing specifications. The DC values indicate the voltage levels at which the final logic state
of the receiver is unambiguously defined. Once the receiver input has crossed the AC value,
the receiver is changed to the new logic state.
The new logic state is maintained as long as the input stays beyond the DC threshold. This
approach is intended to provide predictable receiver timing in the presence of input
waveform ringing.
Figure 1–6. Single-Ended Voltage Referenced I/O Standard
T
t
C
High-speed receiver and transmitter input and output clock period.
TCCS
(channel-to-
channel-skew)
The timing difference between the fastest and the slowest output edges, including t
CO
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to Figure 1–5 under S in this table).
t
DUTY
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =
1/(Receiver Input Clock Frequency Multiplication Factor) = t
C/w)
t
FALL
Signal high-to-low transition time (80-20%)
t
INCCJ
Cycle-to-cycle jitter tolerance on PLL clock input
t
OUTPJ_IO
Period jitter on general purpose I/O driven by a PLL
t
OUTPJ_DC
Period jitter on dedicated clock output driven by a PLL
t
RISE
Signal low-to-high transition time (20–80%)
U
——
Table 1–33. Glossary Table
Letter
Subject
Definitions
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS



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