Chapter 1: DC and Switching Characteristics of HardCopy III Devices

1–13

Switching Characteristics

© December 2008

Altera Corporation

HardCopy III Device Handbook, Volume 3

PLL Specifications

Table 1–19 describes the HardCopy III PLL specifications when operating in both the

commercial junction temperature range (0° to 85° C) and the industrial junction

temperature range (–40° to 100°C). Refer to Figure 1–4 in the “PLL Specifications” row

in Table 1–33 for a PLL block diagram.

Table 1–19. HardCopy III PLL Specifications – Preliminary (Part 1 of 2) (Note 1)

Symbol

Parameter

Min

Typ

Max

Unit

f

IN

Input clock frequency

5

—

717 (2)

MHz

f

INPF D

Input frequency to the PFD

5

—

325

MHz

f

VC O

PLL VCO operating range

600

—

1300

MHz

t

EINDUTY

Input clock or external feedback clock input duty cycle

40

—

60

%

f

OUT

Output frequency for internal global or regional clock

—

—

717 (3)

MHz

f

OUT_EXT

Output frequency for external clock output

—

—

717 (3)

MHz

t

OUTDUTY

Duty cycle for external clock output (when set to 50%)

45

50

55

%

t

FC OMP

External feedback clock compensation time

—

—

10

ns

t

CONF IGPLL

Time required to reconfigure PLL scan chain

—

—

—

scanclk cycles

t

CONF IGPHAS E

Time required to reconfigure phase shift

—

—

—

scanclk cycles

f

SC ANC LK

scanclk

frequency

—

—

100

MHz

t

LOCK

Time required to lock from end of device power up (4)

——

—

ms

t

DLOCK

Time required to lock dynamically (after switchover or

reconfiguring any non-post-scale counters/delays)

——

—

ms

f

CLB W

PLL closed-loop low bandwidth

—

—

—

MHz

PLL closed-loop medium bandwidth

—

—

—

MHz

PLL closed-loop high bandwidth (5)

——

—

MHz

t

PLL_P SERR

Accuracy of PLL phase shift

—

—

—

ps

t

ARES ET

Minimum pulse width on areset signal

10

—

—

ns

t

INCC J (4)

Input clock cycle to cycle jitter (F

—

—

—

UI (p–p)

Input clock cycle to cycle jitter (F

—

—

—

ps (p–p)

t

OUTPJ _DC (6)

Period jitter for dedicated clock output (F

—

—

—

ps (p–p)

Period jitter for dedicate clock output (F

—

—

—

mUI (p–p)

t

OUTCC J_DC (6)

Cycle to cycle jitter for dedicated clock output (F

—

—

—

ps (p–p)

Cycle to cycle jitter for dedicated clock output (F

—

—

—

mUI (p–p)

t

OUTPJ _IO (6)

Period jitter for clock output on regular I/O (F

—

—

—

ps (p–p)

Period jitter for clock output on regular I/O (F

—

—

—

mUI (p–p)

t

OUTCC J_IO (6)

Cycle to cycle jitter for clock output on regular I/O (F

100 MHz)

——

—

ps (p–p)

Cycle to cycle jitter for clock output on regular I/O (F

100 MHz)

——

—

mUI (p–p)