1–20

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

HardCopy III Device Handbook, Volume 3

© December 2008

Altera Corporation

DLL and DQS Logic Block Specifications

Table 1–29 describes the delay-locked loop (DLL) frequency range specifications for

HardCopy III devices.

Table 1–30 describes the DQS phase offset delay per setting for HardCopy III devices.

OCT Calibration Block Specifications

Table 1–31 shows the on-chip termination calibration block specifications for

HardCopy III devices.

Table 1–29. HardCopy III DLL Frequency Range Specifications – Preliminary (Note 1)

Frequency Mode

Frequency Range (MHz)

Resolution (Degrees)

0TBD

22.5

1TBD

30

2TBD

36

3TBD

45

4TBD

30

5TBD

36

6TBD

45

Note to Table 1–29:

(1) Pending silicon characterization.

Table 1–30. Average DQS Phase Offset Delay per Setting – Preliminary (Note 1), (2), (3), (4)

Min

Typ

Max

Unit

711

15

ps

Notes to Table 1–30:

(1) The valid settings for phase offset are –64 to +63 for frequency modes 0 to 3 and –32 to +31 for frequency modes

4 to 6.

(2) The typical value equals the average of the minimum and maximum values.

(3) The delay settings are linear with a cumulative delay variation of ±20ps for all speed grades.

(4) Pending silicon characterization.

Table 1–31. On-Chip Termination Calibration Block Specification – Preliminary

Symbol

Description

Min

Typical

Max

Unit

OCTUSRCLK

Clock required by OCT calibration blocks

—

—

20

MHz

t

OCTC AL

Number of OCTUSRCLK clock cycles required for OCT RS and

RT calibration

—

1000

—

cycles

t

OCTS HIFT

Number of OCTUSRCLK clock cycles required for OCT code to

shift out per OCT calibration block

—

28

—

cycles

t

RS_RT

Time required to dynamically switch from R

—2.5

—

ns