1–16

Chapter 1: DC and Switching Characteristics of HardCopy III Devices

Switching Characteristics

HardCopy III Device Handbook, Volume 3

© December 2008

Altera Corporation

JTAG Specifications

Table 1–22 shows the JTAG timing parameters and values for HardCopy III devices.

Refer to Figure 1–3 in the “HIGH-SPEED I/O Block” row in Table 1–33 for JTAG

timing requirements.

Periphery Performance

This section describes the periphery performance, including high-speed I/O, external

memory interface, and OCT calibration block specifications.

M144K

True dual-port 16K × 9 or 8K × 18, dual clock

1

300

MHz

True dual-port 4K × 36 dual clock

1

430

MHz

Simple dual-port 16K × 9 or 8K × 18, dual clock

1

300

MHz

Simple dual-port 4K × 36 or 2K × 72, dual clock

1

470

MHz

ROM 1 Port

1

500

MHz

ROM 2 Port

1

450

MHz

Single-port 16K × 9 or 8K × 18

1

330

MHz

Single-port 4K × 36

1

500

MHz

True dual-port 16K × 9, 8K × 18, or 4K × 36, dual clock with the

read-during-write option set to “Old Data”

1270

MHz

Simple dual-port 16K × 9, 8K × 18, 4K × 36, or 2K × 72, dual clock with the

read-during-write option set to “Old Data”

1292

MHz

Simple dual-port 2K × 64 dual clock (with ECC)

1

210

MHz

Min Pulse Width (Clock High Time)

—

1000

ps

Note to Table 1–21:

(1) Pending silicon characterization.

Memory

Block Type

Mode

TriMatrix

Memory

Max

Unit

Table 1–22. HardCopy III JTAG Timing Parameters and Values – Preliminary

Symbol

Parameter

Min

Max

Unit

t

JC P

TCK clock period

30

—

ns

t

JC H

TCK clock high time

14

—

ns

t

JC L

TCK clock low time

14

—

ns

t

JTAG port setup time for TDI

1

—

ns

t

JTAG port setup time for TMS

3

—

ns

t

JP H

JTAG port hold time

5

—

ns

t

JP CO

JTAG port clock to output

—

11

ns

t

JP ZX

JTAG port high impedance to valid output

—

14

ns

t

JP XZ

JTAG port valid output to high impedance

—

14

ns