MPC8379ECVRALDA datasheet(73/114 Pages) FREESCALE

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MPC8379E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

NOTE

Figure 53 to Figure 56 below are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance, and

termination requirements are different between various clock driver chip

manufacturers, it is very possible that the clock circuit reference designs

provided by the clock driver chip vendor are different from what is shown

below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver

reference circuits, nor guarantee the correctness of the following clock

driver connection reference circuits. The system designer is recommended

to contact the selected clock driver chip vendor for the optimal reference

circuits with the device SerDes reference clock receiver requirement

provided in this document.

Figure 53 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It

assumes that the DC levels of the clock driver chip is compatible with device SerDes reference clock

input’s DC requirement.

Figure 53. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

Figure 54 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common mode voltage is higher than the device SerDes reference clock input’s

allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

Clock driver vendor dependent

source termination resistor

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

HCSL CLK Driver Chip

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

MPC8379E

CLK_Out

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