MPC8379ECVRALDA datasheet(110/114 Pages) FREESCALE

110 / 114 page

MPC8379E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

110

Freescale Semiconductor

Ordering Information

The value of this resistance and the strength of the driver’s current source can be found by making two

measurements. First, the output voltage is measured while driving logic 1 without an external differential

termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured

while driving logic 1 with an external precision differential termination resistor of value Rterm. The

measured voltage is V2 =(1/(1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource =

Rterm × (V1/V2 – 1). The drive current is then Isource =V1/Rsource.

Table 79 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,

nominal OVDD, 105°C.

24.5

Configuration Pin Muxing

The device provides the user with power-on configuration options which can be set through the use of

external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible configuration

pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins

while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is

disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections

to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should

minimize the disruption of signal quality or speed for output pins thus configured.

24.6

Pull-Up Resistor Requirements

The device requires high resistance pull-up resistors (10 k

Ω is recommended) on open drain type pins

including I2C pins, Ethernet Management MDIO pin and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface,

see AN3665, “MPC837xE Design Checklist.”

25 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 25.1, “Part Numbers Fully Addressed by This Document.”

Table 79. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(not including PCI

output clocks)

PCI Output Clocks

(including

PCI_SYNC_OUT)

DDR DRAM

Symbol

Unit

42 Target

25 Target

42 Target

20 Target

42 Target

25 Target

42 Target

20 Target

Differential

ZDIFF

Note: Nominal supply voltages. See Table 2, Tj = 105°C.

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