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ATmega16HVB 数据表(PDF) 140 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 140 Page - ATMEL Corporation |
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140 / 273 page  140 8042A–AVR–07/09 ATmega16HVB/32HVB 24.6 Battery Protection CPU Interface The Battery Protection CPU Interface is illustrated in Figure 24-2 on page 140. Figure 24-2. Battery Protection CPU Interface Each protection originating from the Current Battery Protection module has an Interrupt Flag. Each Flag can be read and cleared by the CPU, and each flag has an individual interrupt enable. All enabled flags are combined into a single battery protection interrupt request to the CPU. This interrupt can wake up the CPU from any operation mode, except Power-off. The interrupt flags are cleared by writing a logic ‘1’ to their bit locations from the CPU. An interrupt event for the External Protection Input can be generated by enabling the external interrupt for the input port. 24.7 Register Description 24.7.1 BPPLR – Battery Protection Parameter Lock Register • Bit 7:2 – Res: Reserved Bits These bits are reserved bits and will always read as zero. • Bit 1 – BPPLE: Battery Protection Parameter Lock Enable • Bit 0 – BPPL: Battery Protection Parameter Lock The BPCR, BPHCTR, BPOCTR, BPSCTR, BPDHCD, BPCHCD, BPDOCD, BPCOCD and BPSCD Battery Protection registers can be locked from any further software updates. Once 5 / 5 / 10 / Interrupt Request Interrupt Acknowledge FET Control Current Battery Protection Battery Protection Control Register Battery Protection Timing Register Battery Protection Level Register Battery Protection Parameter Lock Register PPI NNI LOCK? LOCK? LOCK? 8-BIT DATA BUS Power-off Battery Protection Interrupt Register Current Protection EXTPROT Bit 765 4321 0 (0xFE) ––– ––– BPPLE BPPL BPPLR Read/Write RR RRRR R/W R/W Initial Value 000 0000 0 |
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