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ATmega16HVB 数据表(PDF) 144 Page - ATMEL Corporation |
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ATmega16HVB 数据表(HTML) 144 Page - ATMEL Corporation |
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144 / 273 page  144 8042A–AVR–07/09 ATmega16HVB/32HVB Notes: 1. The actual value depends on the actual frequency of the ”Ultra Low Power RC Oscillator” on page 27. See ”Electrical Characteristics” on page 228. 2. Initial value. 3. An additional delay T d can be expected after enabling the corresponding FET. This is related to the initialization of the protection circuitry. For the Discharge High-Current protection, this applies when enabling the Discharge FET. For Charge High-Current protection, this applies when enabling the Charge FET. With nominal ULP frequency this delay is maximum 0.2 ms. Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPHCTR register is written. Any writing to the BPHCTR register during this period will be ignored. 24.7.6 BPSCD – Battery Protection Short-circuit Detection Level Register • Bits 7:0 – SCDL7:0: Short-circuit Detection Level These bits sets the R SENSE voltage level for detection of Short-circuit in the Discharge Direction, as defined in Table 24-5 on page 145. Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPSCD register is written. Any writing to the BPSCD register during this period will be ignored. 24.7.7 BPDOCD – Battery Protection Discharge-Over-current Detection Level Register • Bits 7:0 – DOCDL7:0: Discharge Over-current Detection Level These bits sets the R SENSE voltage level for detection of Discharge Over-current, as defined in Table 24-5 on page 145. Note: Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator cycles + 3 CPU clock cycles is required between each time the BPDOCD register is written. Any writing to the BPDOCD register during this period will be ignored. ... ... 0x3E (122 - 124 ms) + T d (3) 0x3F (124 - 126 ms) + Td (3) Table 24-4. High-current Protection Reaction Time. HCPT[5:0] with corresponding High-cur- rent Delay Time. High-current Protection Reaction Time(1) Bit 765 4321 0 (0xF5) SCDL[7:0] BPSCD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 111 1001 1 Bit 765 432 10 (0xF6) DOCDL[7:0] BPDOCD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 0 0 1 1 |
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