ADE7858ACPZ-REF datasheet(49/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 49 of 76

bi(0) =1, i=0, 1, 2,…, 31, the initial state of the bits that form the

CRC. b0 is the less significant bit, b31 is the most significant.

gi, i=0,1,2,…,31 are the coefficients of the generating

polynomial defined by IEEE802.3 standard:

)

(





(45)



(46)

All the other gi coefficients are equal to 0.

)

(

)

(





 

(47)

)

(

)

(





(48)

,...,

(

)

(

)

(













(49)

The operations  and  represent the logic XOR and AND.

The equations (47), (48) and (49) have to be repeated for j=1,

2,…, 256. The value written into CHECKSUM[31:0] register

contains the bits bi(256),i=0,1,…,31. The value of the CRC after

the bits from the reserved internal register have passed through

LFSR is 0x23F7C7B1. It is obtained at step j=48.

Two different approaches may be followed in using the

CHECKSUM register. One is to compute the CRC based on the

relations (45) - (49) and then compare the value against the

CHECKSUM register. Another is to periodically read the

CHECKSUM[31:0] register. If two consecutive readings differ,

then it may be safely assumed that one of the registers has

changed value and therefore, the ADE7858 has changed

configuration. The recommended response is to initiate a

hardware/software reset that sets the values of all registers to the

default, including the reserved ones, and then reinitialize the

configuration registers.

MASK0

MASK1

COMPMODE

GAIN

internal reg

CFMODE

LFSR

generator

internal reg

255

248

240

232

224

216

Figure 56. CHECKSUM[31:0] register calculation

255,a254,...,a2,a1,a0

LFSR

Figure 57.LFSR generator used in CHECKSUM[31:0] register calculation

INTERRUPTS

The ADE7858 has two interrupt pins,

IRQ and

IRQ . Each

of them is managed by a 32-bit interrupt mask register,

MASK0[31:0], respective MASK1[31:0]. To enable an interrupt,

a bit in MASKx[31:0] register has to be set to 1. To disable it, the

bit has to be cleared to 0. Two 32-bit status registers,

STATUS0[31:0] and STATUS1[31:0] are associated with the

interrupts. When an interrupt event occurs in the ADE7858, the

corresponding flag in the interrupt status register is set to a

Logic 1 (see Table 28 and Table 29). If the mask bit for this

interrupt in the interrupt mask register is Logic 1, then the

IRQx logic output goes active low. The flag bits in the interrupt

status register are set irrespective of the state of the mask bits.

To determine the source of the interrupt, the MCU should

perform a read of corresponding STATUSx register and identify

which bit is 1. To erase the flag in the status register, STATUSx

should be written back with the flag set to 1. Practically, after an

interrupt pin goes low, the status register is read and the source

of the interrupt is identified. Then, the status register is written

back without any change to cancel the status flag. The IRQx pin

remains low until the status flag is cancelled.

By default, all interrupts are disabled. RSTDONE interrupt is an

exception. This interrupt can never be masked (disabled) and

therefore bit 15 (RSTDONE) in MASK1[31:0] register does not

have any functionality.

IRQ pin always goes low and bit 15

(RSTDONE) in STATUS1[31:0] is set to 1 whenever a power up

or a hardware/software reset process ends. To cancel the status

ADE7858ACPZ-REF 数据表(PDF) 49 Page - Analog Devices

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