ADE7858ACPZ-REF datasheet(13/76 Pages) AD

13 / 76 page

Preliminary Technical Data

ADE7858

Rev. PrA | Page 13 of 76

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the

ADE7858 is defined by

100

–





Energy

True

Energy

True

ADE7

Registered

Energy

Error

Measuremen

(1)

Phase Error Between Channels

The high-pass filter (HPF) and digital integrator introduce a

slight phase mismatch between the current and the voltage

channel. The all-digital design ensures that the phase matching

between the current channels and voltage channels in all three

phases is within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°

over a range of 40 Hz to 1 kHz. This internal phase mismatch

can be combined with the external phase error (from current

sensor or component tolerance) and calibrated with the phase

calibration registers.

Power Supply Rejection (PSR)

This quantifies the ADE7858 measurement error as a

percentage of reading when the power supplies are varied. For

the ac PSR measurement, a reading at nominal supplies (3.3 V)

is taken. A second reading is obtained with the same input

signal levels when an ac signal (TBD mV rms/TBD Hz) is

introduced onto the supplies. Any error introduced by this ac

signal is expressed as a percentage of reading—see the

Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies

(3.3 V) is taken. A second reading is obtained with the same

input signal levels when the power supplies are varied ±10%.

Any error introduced is again expressed as a percentage of the

reading.

ADC Offset Error

This refers to the dc offset associated with the analog inputs to

the ADCs. It means that with the analog inputs connected to

AGND that the ADCs still see a dc analog input signal. The

magnitude of the offset depends on the gain and input range

selection (see the Typical Performance Characteristics section).

However, the offset is removed from the current and voltage

channels by a HPF and the power calculation is not affected by

this offset.

Gain Error

The gain error in the ADCs of the ADE7858 is defined as the

difference between the measured ADC output code (minus the

offset) and the ideal output code (see the Current Channel ADC

section and the Voltage Channel ADC section). The difference

is expressed as a percentage of the ideal code.

Gain Error Match

The gain error match is defined as the gain error (minus the

offset) obtained when switching between a gain of 1, 2, 4, 8 or

16. It is expressed as a percentage of the output ADC code

obtained under a gain of 1.

CF Jitter

The period of pulses at one of CF1, CF2 or CF3 pins is

continuously measured. The maximum, minimum and average

values of 4 consecutive pulses are computed:

)

max(

Period

MAX



)

min(

Period

MIN



Period

AVG





The CF jitter is then computed as

[%]

100







AVG

MIN

MAX

CF jitter

(2)

ADE7858ACPZ-REF 数据表(PDF) 13 Page - Analog Devices

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