ADE7858ACPZ-REF datasheet(21/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 21 of 76

















Gain

Current

Content

Output

waveform

Current

(3)

Changing the content of AIGAIN[23:0], BIGAIN[23:0] or

CIGAIN[23:0] affects all calculations based on its current; that

is, it affects the corresponding phase active/reactive/apparent

energy and current rms calculation. In addition, waveform

samples are also scaled accordingly.

Note that the serial ports of the ADE7858 work on 32, 16 or 8-

bit words and the DSP works on 28 bits. The 24-bit AIGAIN,

BIGAIN and CIGAIN registers are accessed as 32-bit registers

with 4 most significant bits padded with 0s and sign extended

to 28 bits. See Figure 15 for details.

24 bit number

0000

bit 23 is sign bit

bits 27-24 equal

to bit 23

Figure 15. 24-bit xIGAIN (x=A,B,C,N) are transmitted as 32-bit words

Current Channel HPF

The ADC outputs can contain a dc offset. This offset may

create errors in power and rms calculations. High Pass Filters

(HPF) are placed in the signal path of the phase and neutral

currents and of the phase voltages. If enabled, the HPF

eliminates any dc offset on the current channel. All filters are

implemented in the DSP and by default they are all enabled: 24-

bit register HPFDIS[23:0] is cleared to 0x00000000. All filters

are disabled by setting HPHDIS[23:0] to any non zero value.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words. The HPFDIS register is accessed as a 32-

bit register with 8 most significant bits padded with 0s. See

Figure 16 for details.

24 bit number

0000 0000

Figure 16. 24-bit HPFDIS register is transmitted as 32-bit word

Current Channel Sampling

The waveform samples of the current channel are taken at the

output of HPF and stored into IAWV, IBWV, ICWV 24-bit

signed registers at a rate of 8kSPS. All power and rms

calculations remain uninterrupted during this process. Bit 17

(DREADY) in STATUS0[31:0] register is set when IAWV,

IBWV and ICWV registers are available to be read using I2C or

SPI serial ports. Setting bit 17 (DREADY) in MASK0[31:0]

set. See Digital Signal Processor chapter for more details on bit

DREADY.

IAP

IAN

PGA1

ADC

PGA1 bits

GAIN[2:0]

x1, x2, x4,x8,

x16

REFERENCE

AIGAIN[23:0]

HPF

DIGITAL

INTEGRATOR

INTEN bit

CONFIG[0]

CURRENT RMS (IRMS)

CALCULATION

IAWV WAVEFORM

SAMPLE REGISTER

TOTAL ACTIVE

POWER CALCULATION

+0.5V/GAIN

-0.5V/GAIN

ANALOG INPUT RANGE

0x5A7540=

5,928,256

0xA58AC0=

-5,928,256

ADC OUTPUT RANGE

CURRENT CHANNEL

DATA RANGE

CURRENT CHANNEL

DATA RANGE AFTER

INTEGRATOR

DSP

ZX SIGNAL

DATA RANGE

CURRENT PEAK,

OVERCURRENT

DETECT

LPF1

ZX DETECTION

0x5A7540=

5,928,256

0xA58AC0=

-5,928,256

0x5A7540=

5,928,256

0xA58AC0=

-5,928,256

HPFDIS[23:0]

Figure 17. Current Channel Signal Path

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