ADE7858ACPZ-REF datasheet(17/76 Pages) AD

17 / 76 page

Preliminary Technical Data

ADE7858

Rev. PrA | Page 17 of 76

active serial port, bit 1 (I2C_LOCK) of CONFIG2[7:0] must be

set to 1 to lock it in. From this moment on, the ADE7858

ignores spurious togglings of the SS pin and an eventual switch

into using SPI port is no longer possible. If SPI is the active

serial port, any write to CONFIG2[7:0] registers locks the port.

From this moment on, a switch into using I2C port is no longer

possible. Only a power down or setting RESET pin low resets

back the ADE7858 to use the I2C port. Once locked, the serial

port choice is maintained when the ADE7858 changes PSMx,

x=0, 1, 2, 3 power modes.

Immediately after entering PSM0, the ADE7858 sets all

registers to their default values, including CONFIG2[7:0]. The

ADE7858 signals the end of the transition period by triggering

IRQ interrupt pin low and setting bit 15 (RSTDONE) in

STATUS1[31:0] register to 1. This bit is 0 during the transition

period and becomes 1 when the transition ends. The status bit

is cleared and

IRQ pin is set back high by writing

STATUS1[31:0] register with the corresponding bit set to 1. As

the RSTDONE is an unmaskable interrupt, bit 15 (RSTDONE)

in STATUS1[31:0] register has to be cancelled in order for

the

IRQ pin to turn back high. It is recommended to wait until

IRQ pin goes low before accessing STATUS1[31:0] register to

test the state of RSTDONE bit. At this point, as a good

programming practice, it is also recommended to cancel all

other status flags in STATUS1[31:0] and STATUS0[31:0]

registers by writing the corresponding bits with 1.

Initially, the DSP is in idle mode, which means it does not

execute any instruction. This is the moment to initialize all

ADE7858 registers and then write 0x0001 into the RUN[15:0]

for details on the RUN[15:0] register).

If the supply voltage VDD becomes lower than 2V ± 10%, the

ADE7858 goes into inactive state, which means no

measurements and computations are executed.

Hardware Reset

The ADE7858 has a RESET pin. If the ADE7858 is in PSM0

mode and RESET pin is set low, then the ADE7858 enters in

hardware reset state. The ADE7858 has to be in PSM0 mode

for hardware reset to be considered. Setting RESET pin low

while the ADE7858 is in PSM1, PSM2 and PSM3 modes does

not have any effect.

If the ADE7858 is in PSM0 mode and RESET pin is toggled

from high to low and then back high after at least 10μsec, all the

registers are set to their default values, including

CONFIG2[7:0]. The ADE7858 signals the end of the transition

period by triggering

IRQ interrupt pin low and setting bit 15

(RSTDONE) in STATUS1[31:0] register to 1. This bit is 0

during the transition period and becomes 1 when the transition

ends. The status bit is cleared and

IRQ pin is set back high by

writing STATUS1[31:0] register with the corresponding bit set

to 1.

After a hardware reset, the DSP is in idle mode, which means it

does not execute any instruction. As the I2C port is the default

serial port of the ADE7858, it becomes active after a reset state.

If SPI is the port used by the external microprocessor, the

procedure to enable it has to be repeated immediately after

RESET pin is toggled back high. See Serial Interfaces chapter

for details.

At this point, it is recommended to initialize all ADE7858

registers and then write 0x0001 into the RUN[15:0] register to

start the DSP (see Digital Signal Processor chapter for details on

RUN[15:0] register).

Software Reset Functionality

Bit 7 (SWRST) in CONFIG[15:0] register manages the software

reset functionality in PSM0 mode. The default value of this bit

is 0. If this bit is set to 1, then the ADE7858 enters a software

reset state. In this state, almost all internal registers are set to

their default value. In addition, the choice of what serial port

I2C or SPI is in use remains unchanged if the lock in procedure

has been previously executed (See Serial Interfaces chapter for

details). The register that maintains its value despite SWRST bit

being set to 1 is CONFIG2[7:0]. When the software reset ends,

bit 7 (SWRST) in CONFIG[15:0] is cleared to 0, the

IRQ

interrupt pin is set low and bit 15 (RSTDONE) in

STATUS1[31:0] register is set to 1. This bit is 0 during the

transition period and becomes 1 when the transition ends. The

status bit is cleared and

IRQ pin is set back high by writing

STATUS1[31:0] register with the corresponding bit set to 1.

After a software reset ended, the DSP is in idle mode, which

means it does not execute any instruction. It is recommended to

initialize all the ADE7858 registers and then write 0x0001 into

the RUN[15:0] register to start the DSP (see Digital Signal

Processor chapter for details on the RUN[15:0] register).

Software reset functionality is not available in PSM3 mode.

Table 8: ADE7858 Power modes and related characteristics

Power

Mode

Registers

CONFIG2

I2C/SPI

Functionality

PSM0

State after

hardware reset

Set to

default

Set to default

I2C enabled

-All circuits are active. DSP is in

idle mode.

State after

software reset

Set to

default

Unchanged

Active serial port unchanged if lock

in procedure has been previously

-All circuits are active. DSP is in

idle mode.

ADE7858ACPZ-REF 数据表(PDF) 17 Page - Analog Devices

ADE7858ACPZ-REF 数据表(HTML) 17 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载