ADE7858ACPZ-REF datasheet(20/76 Pages) AD

20 / 76 page

ADE7858

Preliminary Technical Data

Rev. PrA| Page 20 of 76

quantization noise (noise due to sampling) over a wider

bandwidth. With the noise spread more thinly over a wider

bandwidth, the quantization noise in the band of interest is

lowered — see Figure 13. However, oversampling alone is not

efficient enough to improve the signal-to-noise ratio (SNR) in

the band of interest. For example, an oversampling ratio of 4 is

required just to increase the SNR by only 6 dB (1 bit). To keep

the oversampling ratio at a reasonable level, it is possible to

shape the quantization noise so that the majority of the noise

lies at the higher frequencies. In the -Δ modulator, the noise is

shaped by the integrator, which has a high-pass-type response

for the quantization noise. This is the second technique used to

achieve high resolution. The result is that most of the noise is at

the higher frequencies where it can be removed by the digital

low-pass filter. This noise shaping is shown in Figure 13.

NOISE

SIGNAL

Digital Filter

Antialias Filter

(RC)

Sampling

Frequency

Shaped Noise

1024

512

Frequency [KHz]

NOISE

SIGNAL

High Resolution

Output From

Digital LPF

Frequency [KHz]

512

1024

Figure 13. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

Antialiasing Filter

Figure 12 also shows an analog low-pass filter (RC) on the input

to the ADC. This filter is placed outside the ADE7858 and its

role is to prevent aliasing. Aliasing is an artifact of all sampled

systems and is illustrated in Figure 14. Aliasing means that

frequency components in the input signal to the ADC, which

are higher than half the sampling rate of the ADC, appear in the

sampled signal at a frequency below half the sampling rate.

Frequency components (arrows shown in black) above half the

sampling frequency (also know as the Nyquist frequency, i.e.,

512 kHz) are imaged or folded back down below 512 kHz. This

happens with all ADCs regardless of the architecture. In the

example shown, only frequencies near the sampling frequency,

i.e., 1.024MHz, move into the band of interest for metering, i.e.,

40 Hz to 2 kHz. To attenuate the high frequency (near

1.024MHz) noise and prevent the distortion of the band of

interest, a LPF (low-pass filter) has to be introduced. For

conventional current sensors, it is recommended to use one RC

filter with a corner frequency of 5 KHz in order for the

attenuation to be sufficiently high at the sampling frequency of

1.024MHz. The 20 dB per decade attenuation of this filter is

usually sufficient to eliminate the effects of aliasing for

conventional current sensors. However, for a di/dt sensor such

as a Rogowski coil, the sensor has a 20 dB per decade gain. This

neutralizes 20 dB per decade attenuation produced by the LPF.

Therefore, when using a di/dt sensor, care should be taken to

offset the 20 dB per decade gain. One simple approach is to

cascade one more RC filter, so a –40 dB per decade attenuation

is produced.

Sampling

Frequency

1024

Frequency [KHz]

ALIASING EFFECTS

IMAGE

FREQUENCIES

512

Figure 14. Aliasing effects at ADE7858

ADC Transfer Function

All ADCs in the ADE7858 are designed to produce the same

24-bit signed output code for the same input signal level. With a

full-scale input signal of 0.5 V and an internal reference of 1.2 V,

the ADC output code is nominally 5,928,256 (0x5A7540). The

code from the ADC may vary between 0x800000 (-8,388,608)

and 0x7FFFFF (+8,388,607); this is equivalent to an input signal

level of ±0.707V. However, for specified performance, it is

recommended not to exceed the nominal range of ±0.5V. The

ADC performance is guaranteed only for input signals lower

than ±0.5V.

CURRENT CHANNEL ADC

Figure 17 shows the ADC and signal processing path for the

input IA of the current channels (same for IB and IC). The

ADC outputs are signed twos complement 24-bit data-words

and are available at a rate of 8 kSPS (thousand samples per

second). With the specified full-scale analog input signal of

±0.5V, the ADC produces its maximum output code value. This

diagram shows a full-scale voltage signal being applied to the

differential inputs IAP and IAN. The ADC output swings

between −5,928,256 (0xA58AC0 ) and+5,928,256 (0x5A7540).

Current Waveform Gain Registers

There is a multiplier in the signal path of each phase current.

The current waveform can be changed by ±100% by writing a

correspondent twos complement number to the 24-bit signed

current waveform gain registers (AIGAIN[23:0], BIGAIN[23:0]

and CIGAIN[23:0]). For example, if 0x400000 is written to

those registers, the ADC output is scaled up by 50%. To scale

the input by -50%, write 0xC00000 to the registers. Equation (3)

describes mathematically the function of the current waveform

gain registers.

ADE7858ACPZ-REF 数据表(PDF) 20 Page - Analog Devices

ADE7858ACPZ-REF 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载

链接网址

ADE7858ACPZ-REF 数据表(PDF) 20 Page - Analog Devices

ADE7858ACPZ-REF 数据表(HTML) 20 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表 下载

链接网址

数据表下载