ADE7858ACPZ-REF datasheet(11/76 Pages) AD

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Preliminary Technical Data

ADE7858

Rev. PrA | Page 11 of 76

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADE7858

TOP VIEW

(not to scale)

VDD

AVDD

DVDD

AGND

DGND

IAP

IAN

IBN

ICP

ICN

VAP

VBP

VCP

IBP

REF

in/out

CLKIN

CLKOUT

SCLK/

SCL

MOSI/

SDA

MISO/

HSD

CF1

CF2

CF3/

HSCLK

PM0

PM1

IRQ

RESET

HSA

Figure 6. ADE7858 Pin Configuration

Table 6. Pin Function Descriptions

No.

Mnemonic

Description

1,10,11,20,21,30,31,40

These pins are not connected internally.

PM0

Power Mode pin 0. For proper operation, this pin should be set to VDD vis a 10kΩ pull-up

resistor.

PM1

Power Mode pin 1. This pin defines the power mode of the ADE7858 as described in Table 7.

RESET

Reset Input, active low. In PSM0, this pin should stay low for at least 10μsec to trigger a

hardware reset

DVDD

This pin provides access to the on-chip 2.5V digital LDO. No external active circuitry should

be connected to this pin. This pin should be decoupled with a 4.7 μF capacitor in parallel

with a ceramic 220 nF capacitor.

DGND

This provides the ground reference for the digital circuitry in the ADE7858.

7,8,

9,12,

13,14,

IAP, IAN,

IBP, IBN,

ICP, ICN,

Analog Inputs for Current Channel. This channel is used with the current transducers and is

referenced in this document as the current channel. These inputs are fully differential

voltage inputs with a maximum differential level of ±0.5 V. This channel has also an internal

PGA, for IAx, IBx and ICx.

15,16

Connect to AGND.

REFIN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a

nominal value of 1.2 V ± 0.075% and a maximum temperature coefficient of 50 ppm/°C. An

external reference source with 1.2V ± 8% can also be connected at this pin. In either case,

this pin should be decoupled to AGND with a 4.7 μF capacitor in parallel with a ceramic

100nF capacitor. After reset, the on-chip reference is enabled.

18, 19,

22, 23

VN, VCP,

VBP, VAP

Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and

is referenced as the voltage channel in this document. These inputs are single-ended

voltage inputs with the maximum signal level of ±0.5 V with respect to VN for specified

operation. This channel has also an internal PGA.

AVDD

This pin provides access to the on-chip 2.5V analog LDO. No external active circuitry should

be connected to this pin. This pin should be decoupled with a 4.7 μF capacitor in parallel

with a ceramic 220 nF capacitor.

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