TUSB1310

SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

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2.4

Clocking

Table 2-5. Clock Signal Name Description

SIGNAL NAME

TYPE

BALL NO.

DESCRIPTION

Crystal Input. This pin is the clock reference input for the TUSB1310. The TUSB1310

XI

I

A12

supports either a crystal unit, or a 1.8-V clock input. Frequencies supported are 20, 25,

30, or 40 MHz.

XO

O

A11

Crystal output. If a 1.8-V clock input is connected to XI, XO must be left open.

CLKOUT

O

D10

OOBCLK is driven in U3 mode.

2.5

JTAG Interface

The JTAG Interface is used for board-level boundary scan. All digital IO support IEEE1149.1 boundary

scan and SuperSpeed differential pairs support IEEE1149.6 boundary scan.

Table 2-6. JTAG Signal Name Description

SIGNAL NAME

TYPE

BALL NO.

DESCRIPTION

JTAG_TCK

I, PU

G11

JTAG test clock

JTAG_TMS

I, PU

D11

JTAG test mode select

JTAG_TDI

I, PU

E11

JTAG test data input

JTAG_TRSTN

I, PD

E12

JTAG test asynchronous reset. Active Low.

JTAG_TDO

O

F11

JTAG test data output

2.6

Reset and Output Control Interface

Table 2-7. Reset and Output Control Signal Description

SIGNAL NAME

TYPE

BALL NO.

DESCRIPTION

RESETN

I

J11

Active Low. Resets the transmitter and receiver. This signal is asynchronous.

Active High. This can be connected to a 1.8-V power on reset signal on the PCB in

order to avoid static current and signal contention during power up.

OUT_ENABLE

I

L10

0: Disable all driver outputs while IO powers are supplied, but internal control circuit

powers are not present during power up.

1: Enable all driver outputs during normal operation.

2.7

Strap Options

Strapping pins are latched by reset de-assertion in the TUSB1310.

Table 2-8. Strapping Options

SIGNAL NAME

TYPE

BALL NO.

DESCRIPTION

Selects an input clock source

XTAL_DIS

S, I/O, PD

F3

0

Crystal Input

(RX_ELECIDLE)

1

Clock Input

Selects PIPE

PIPE_16BIT

S, I/O, PD

E3

0

16-bit PIPE SDR mode

(PHY_STATUS)

Must be 0 at reset.

Active High. Puts PIPE into isolate mode. When in the isolate mode, TUSB1310 does

not respond to packet data present at TX_DATA15-0, TXDATAK1-0 inputs and presents

a high imped-ance on the PCLK, RX_DATA15-0, RX_DATAK1-0, RX_VALID outputs.

ISO_START

S, I/O, PD

N6

When in the isolate mode, the TUSB1310 will continue to respond to ULPI. Once the

(ULPI_DATA7)

isolate mode bit in ULPI register is cleared, the USB interfaces will start transmitting

packet data on TX_DATA15-0 and driving PCLK, RX_DATA15-0, RX_DATA1-0, and

RX_VALID.

14

PIN DESCRIPTIONS

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