TUSB1310

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SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

3.3.1

USB Power Management

The USB 3.0 specification improves power consumption by defining 4 power states, U0, U1, U2, and U3

while the PIPE specification defines P0, P1, P2 and P3. The POWER_DOWN pin states are mapped to

LTSSM states as described in Table 2-10. For all power state transitions, the link layer controller must not

begin any operational sequences or further power state transitions until the TUSB1310 has indicated that

the internal state transition is completed.

Table 3-2. Power States

PIPE

USB POWER

POWER

PCLK

PLL

TRANSMITTING

RECEIVING

PHY_STATUS

STATE

STATE

U0, all other LTSSM

A single cycle

P0

On

On

Active or Idle or LFPS

Active or Idle

states

assertion

A single cycle

P1

U1

On

On

Idle or LFPS

Idle

assertion

U2, RxDetect,

A single cycle

P2

On

On

Idle or LFPS or RxDetect

Idle

SS.Inactive

assertion

PHY_STATUS is

Off. The

asserted before

PIPE is in

PCLK is turned off

P3

U3, SS.disabled

an

Off

LFPS or RxDetect

Idle

and deasserted

asynchrono

when PCLK is fully

us mode

off.

When the link layer controller wants to transmit LFPS in P1, P2, or P3 state, it must de-assert

TX_ELECIDLE. The TUSB1310 generates valid LFPS until the TX_ELECIDLE is asserted. The link layer

controller must assert TX_ELECIDLE before transitioning to P0.

When RX_ELECIDLE is de-asserted in P0, P1, P2, or P3, the TUSB1310 receiver monitors for LFPS

except during reset or when RX_TERMINATION is removed for electrical idle.

When the TUSB1310 is in P0 and is actively transmitting; only RX_POLARITY can be asserted.

Table 3-3. PIPE Control Pin Matrix

POWER STATE

TX_DETRX_LPBK

TX_ELECIDLE

DESCRIPTION

0

0

Transmitting data on TX_DATA

0

1

Not transmitting and is in electrical idle.

P0

1

0

Goes into loopback mode

1

1

Transmits LFPS signaling

0

Transmits LFPS signaling

P1

Don't care

1

Not transmitting and is in electrical idle.

Don't care

0

Transmits LFPS signaling

P2

0

1

Idle

1

1

Does a receiver detection operation

0

Transmits LFPS signaling

P3

Don't care

1

Does a receiver detection operation

3.4

Receiver Status

The TUSB1310 has an elastic buffer for clock tolerance compensation, the link partner detection, and

some received data error detections. The receive data status from SSRXP/SSRXN differential pair

presents on RX_STATUS2-0. If an error occurs during a SKP ordered set, the error signaling has

precedence. If more than one error occurs on a received byte, the errors have the priority below.

1. 8B/10B decode error

2. Elastic buffer overflow

Copyright © 2009–2010, Texas Instruments Incorporated

FUNCTIONAL DESCRIPTION

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