TUSB1310 datasheet(32/36 Pages) TI

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TUSB1310

SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

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6.5.4

ULPI Parameters

Table 6-4. ULPI Parameters

DESCRIPTION

NOTES

UNIT

RX CMD delay

2-4

clocks

TX start delay

1-2

1-10

clocks

TX end delay

PHY pipeline delays

2-5

clocks

RX start delay

3-8

clocks

RX end delay

3-8

17-18

122-123

clocks

Transmit-Transmit (host only)

15-24

7-18

77-247

clocks

Link decision times

Receive-Transmit (host or peripheral)

1-14

7-18

77-247

clocks

6.5.5

ULPI Clock

Table 6-5. ULPI Clock Parameters

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

Fstart_8bit

Frequency (first transition) ±10%

MHz

Fsteady

Frequency (steady state) ±500 ppm

59.97

60.03

MHz

Dstart_8bit

Duty cycle (first transition) ±10%

Dsteady

Duty cycle (steady state) ±500 ppm

49.975

50.025

Tsteady

Time to reach steady state frequency and duty cycle after first transition

1.4

Tstart_dev

Clock startup time after deassertion of SuspemdM – Peripheral

5.6

Tstart_host

Clock startup time after deassertion of SuspemdM – Hold

Tprep

PHY preparation time after first transition of input clock

µs

Tjitter

Jitter

Trise/Tfall

Rise and fall time

6.5.6

ULPI Transmit

Figure 6-4. ULPI Transmit Timing

ELECTRICAL SPECIFICATIONS

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