Power Supplies

XI

RESETN

PCLK

ULPI_CLK

Internal resetn/

PLL_EN/

SUSPENDM

Internal latched

strapping pin states

Latched data

PHY_STATUS/

ULPI_DIR

300ms

TUSB1310

SLLSE16C – DECEMBER 2009 – REVISED AUGUST 2010

www.ti.com

Figure 3-1. Power Up Sequence

After proper power supply sequencing, the reference clock on XI starts to operate. On the RESETN

de-assertion, REFCLKSEL1-0 is determined depending on the PHY_MODE pins, PLL is locked and the

valid ULPI_CLK and the valid PCLK are driven.

After all stable clocks are provided, the TUSB1310 allows the link layer controller to access by

de-asserting the ULPI_DIR. The link layer controller sets the Reset bit in the ULPI register. At the PIPE

in-terface, the PHY_STATUS changes from high to low in order to indicate the TUSB1310 is in the power

state specified by the POWER_DOWN signal. After the PHY_STATUS change, the TUSB1310 is ready

for PIPE transactions.

3.2

Clocks

3.2.1

Clock Distribution

A source clock should be provided via XI/XO from an external crystal or from a square wave clock. The

USB3.0 PLL provides a clock to the PIPE which drives 250 MHz. The USB2.0 PLL provides a 60-MHz

clock to the ULPI.

3.2.2

Output Clock

The CLKOUT is used by the link layer controller or the MAC. When ClkoutEn bit at the ULPI SS USB

register is set low, a 120-MHz clock is available via the CLKOUT only in the USB U3 power state. If the

ClkoutEn bit is set high, the 250-MHz clock is driven via CLKOUT in all power states.

3.3

Power Management

The SuperSpeed USB power state transition is controlled by the PIPE POWER_DOWN1-0 and the

non-SuperSpeed USB power state is transitioned by setting suspendM bit in the ULPI Function control

register via the ULPI or by asserting the ULPI_STP.

18

FUNCTIONAL DESCRIPTION

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